1. Field of the Invention
The present invention relates to a transistor operating at a low power supply voltage by dynamically varying a threshold value, a semiconductor device including such transistors, and a method for producing such a semiconductor device. The present invention also relates to a contact formation technique for the transistors and an element separation technique suitable for integration of the transistor elements.
2. Description of the Releted Art
The power consumption of a circuit, in which MOS transistors of different conductivity types are complementarily connected to each other (a CMOS circuit), increases in proportion to the square of a power supply voltage. Therefore, it is effective to reduce the power supply voltage for reduction of the power consumption of a large scale integrated circuit (LSI) formed by using CMOS circuits. However, since the driving power of transistors is reduced simultaneously with the reduction of the power supply voltage, the delay time of the LSI circuit is disadvantageously increased. The delay time is increased as the power supply voltage is lowered. In particular, it is known that, when a power supply voltage becomes lower than three times as much as a threshold voltage (i.e., 3×Vth), the delay time remarkably increases.
As a method for solving this problem, it is conceived to set a threshold voltage of the transistor to be low. However, if a threshold voltage is set at a low value, there arises a problem that a leak current during gate-OFF increases. Accordingly, the lower limit of the threshold voltage is limited depending on the acceptable degree of an OFF current (leak current).
In order to alleviate this problem, a dynamic threshold voltage operating transistor for effectively lowering a threshold voltage during gate ON has been proposed as a transistor corresponding to a low power supply voltage (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, F. Assaderaghi et al., IEDM94 Ext. Abst. pp.809).
A conventional structure of such a transistor is shown in FIG. 53. Although an N-channel MOS transistor (NMOS) is shown in FIG. 53, it is possible to construct a P-channel MOS transistor (PMOS) by providing an opposite polarity for the respective regions. This transistor is built on a Silicon-On-Insulator (SOI) substrate. A gate electrode and the substrate (a region of a silicon layer) are short-circuited through a local wiring by using an oversized metal wiring. In such a structure where the gate electrode and the substrate are short-circuited, when a bias voltage (a gate bias) is applied to the gate electrode, a forward bias as large as the gate bias is applied to an active region of the substrate.
However, in order to restrain the standby current in such a structure, the voltage to be applied to the gate electrode should be limited to below 0.6 V at which a lateral parasitic bipolar transistor is turned ON. In this manner, the same bias state as that in a normal transistor is formed during gate-OFF, and the substrate is forward biased as the gate bias increases during gate ON. As a result, a threshold voltage is reduced during gate ON.
As a result, the leak current during gate-substrate bias OFF is the same as that in a normal SOI transistor in the same channel state. When the transistor is an ON state, the threshold voltage is lowered as the gate-substrate bias is increased. Thus, the gate overdrive effect is increased to remarkably increase the driving power. A mobility is prevented from being deteriorated by the restraint of a longitudinal electric field on the surface of the substrate, which serves to increase the driving power. Since a lateral parasitic bipolar transistor is in an OFF state, the standby current is prevented from being remarkably increased.
Since the SOI substrate is utilized in the conventional technique described above, an active layer substrate is perfectly electrically insulated. Therefore, as compared with a device formed on a bulk substrate, holes generated in a channel (electrons in the case of a PMOS) are likely to be accumulated. As a result, the generation of kink in a drain current due to a substrate floating effect or characteristic hysteresis effect becomes a problem.
Moreover, the electrical insulation of the active layer substrate creates the problem of charge-up or causes electrostatic damage (ESD) to be generated during the fabrication process.
Furthermore, in the case where a separation by implanted oxygen (SIMOX) substrate, which has the best crystallinity at present, is used instead of the SOI substrate, the deterioration of characteristics due to carrier implantation to the bottom interface or capture becomes a problem. This is because the interface between the buried oxide film and the substrate has a larger degree of disturbance of the bonding state than that in the interface between the gate oxide film and the substrate on the channel side.
Furthermore, since a body (channel region) has an extremely small thickness (about 50 nm to about 200 nm) with the SOI substrate, the resistance becomes remarkably high. Therefore, even if the gate and the body are to be short-circuited by a contact region, it becomes more difficult to transfer a potential to the body as the distance from the contact increases. Therefore, the effect of a DTMOS is not fully demonstrated.